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Evaluation driven layout synthesis

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3 Author(s)
A. C. -H. Wu ; Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA ; D. D. Gajski ; G. -D. Chen

The authors describe a layout synthesis system for layout generation from generalized register-transfer schematics. This system uses the SLAM partitioner and the ICDB component server. The system is performed in a completely top-down manner which generates the layout by considering the component layout style, floorplan, and critical paths simultaneously. This improves the overall area utilization and minimizes the critical wire lengths, which in turn yields better performance

Published in:

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Date of Conference:

22-24 May 1991