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A microprocessor-based dot matrix display system for Japanese Hiragana syllables

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2 Author(s)
Goh, W.L. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore ; Lau, K.T.

A microprocessor-based 5×7 dot-matrix display system for Japanese Hiragana syllables is proposed. The dot-matrix layout for each of the 68 syllables is shown. The syllable generation or the selective dots to produce a display is accomplished using a column approach, i.e. 7 dots (comprising one column) are displaced at a time with proper multiplexing, the display of each syllable is completed in 5 steps. A complete Hiragana word typically comprises one to four syllables. A four-syllable string (i.e., four 5×7 dot-matrix displays) display system is therefore proposed. The organization of the microprocessor-based hardware for such a display system is discussed and the system flowchart is given. Each character in the string is presented as a 7-bit ASCII code to the microprocessor. A program compares the character string that is input and selects the appropriate Hiragana syllables for display from a look-up table of bit patterns stored in memory. As each Hiragana syllable requires (5×7)+35 dots (or bits), five bytes of data are used to represent one syllable, ignoring the last bit of each byte. To represent the full 68 Hiragana syllables, a total of 340 bytes of memory locations are required

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:35 ,  Issue: 1 )

Date of Publication:

Feb 1989

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