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Flexible timing specification in a VHDL synthesis subset

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3 Author(s)
A. Stoll ; Corp. Res. & Dev., Siemens AG, Munchen, Germany ; J. Biesenack ; S. Rumler

A VHSIC hardware description language (VHDL) subset for high-level synthesis allowing a flexible timing specification of the circuit interface such that the optimization potential of classical scheduling and allocation techniques can be fully used is presented. The algorithmic circuit specification can be validated by a conventional VHDL simulator if the description style follows the proposed guidelines. This validation depends on the proper description style, but methods of timing specification allow an adequate low-level description of higher communication primitives such as the input and output commands

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992