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Design verification considering manufacturing tolerances by using worst-case distances

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3 Author(s)
H. E. Graeb ; Inst. of Electron. Design Autom., Tech. Univ. of Munich, Germany ; C. U. Wieser ; K. J. Antreich

A new method for design verification on circuit level considering the inevitable manufacturing tolerances is presented. It is based on a specific backward evaluation of performance specifications, which can be done efficiently with a sequential quadratic programming method using standard simulation tools. The specific backward evaluation yields exact worst-case parameter sets and corresponding worst-case distances for all specifications separately. Automatic circuit quality analysis enables a detailed design verification and supports the circuit design process by planning aids for a design step. The various features of the method are illustrated using a small tutorial circuit example. A practical example of an integrated CMOS analog circuit proves the efficiency of the new approach

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992