Referenced Items are not available for this document.
A performance-driven approach to module generation, called PERFLEX, for static combinational CMOS logic circuits is described. The flexible layout style supports implementation of fast and reliable circuits. Improvement in circuit speed is achieved through minimization of diffusion and interconnection capacitance, transistor sizing, and transistor reordering. By integrating transistor sizing and reordering steps in the layout process, fine-grain optimization is achieved. Experimental results are presented
Published in:
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Date of Conference: 7-10 Sep 1992
- Page(s):
- 154 - 159
- Meeting Date :
- 07 Sep 1992-10 Sep 1992
- Print ISBN:
- 0-8186-2780-8
- INSPEC Accession Number:
- 4493510
- Conference Location :
- Hamburg
- Digital Object Identifier :
- 10.1109/EURDAC.1992.246249
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
