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Automatic partitioning for deterministic test

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5 Author(s)
D. Crestani ; UMR CNRS, Montpellier II Univ., France ; A. Aguila ; M. K. Gentil ; P. Chardon
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Automatic partitioning for digital circuits is proposed. The partitions are defined by using functional testability measures and a test difficulty estimation. The software, developed with an expert system generator, is embedded in a hierarchical test generation process. The partitioning technique proposed uses difficulty test estimation corresponding to the maximal number of logical gates that can be embedded in a given partition. This parameter represents the maximal number of gates that can be handled by the tool

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992