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Automatic module allocation in high level synthesis

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4 Author(s)
Gutberlet, P. ; Forschungszentrum Inf., Karlsruhe, Germany ; Muller, J. ; Kramer, H. ; Rosenstiel, W.

A main step in high-level synthesis is data-path synthesis consisting of allocation, scheduling and assignment. The authors present an allocation algorithm designed for an environment where the allocation precedes scheduling and assignment. This algorithm selects the hardware components (in type and number) fully automatically and supports a realistic area/time tradeoff. During this allocation a design space exploration is performed. The allocation is separated from the scheduling and assignment, allowing very efficient implementation

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992