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A performance driven generator for efficient testable conditional-sum-adders

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2 Author(s)
B. Becker ; Dept. of Comp. Sci., Johann Wolfgang Goethe-Univ., Frankfurt, Germany ; P. Molitor

The authors present a performance driven generator for integer adders which is parameterized in n, the operands' bit length, tn, the delay of the addition, and FM, the (cell based static) fault model. FM may in particular be chosen as the classical stuck-at fault model or the cellular fault model. The output of the generator is an area-minimal n-bit adder of the conditional-sum type with delay ⩽tn (if such a circuit exists at all). The number of test vectors constructed is bounded by O(n2). The running time of the generator itself is about c×n2× tn where c is a small constant

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992