By Topic

Willow: a scalable shared memory multiprocessor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
J. K. Bennett ; Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA ; S. Dwarkadas ; J. Greenwood ; E. Speight

The authors are currently developing Willow, a shared memory multiprocessor whose design provides system capacity and performance capable of supporting over 1000 commercial microprocessors. Recently, they have focused their attention on the design of a 64-processor prototype that tests most of their ideas about scalability. In this paper, they describe the factors that traditionally limited the scalability of shared memory systems. These include enforcing sequential consistency, inefficient synchronization, memory latency and bandwidth limitations, bus and memory contention, the necessity to enforce inclusion on lower-level caches, and limited I/O (input/output) bandwidth. They then describe how the Willow architecture addresses each of these issues. Finally, they present data in order to evaluate the effect of the major architectural innovations in Willow on the performance of several parallel applications

Published in:

Supercomputing '92., Proceedings

Date of Conference:

16-20 Nov 1992