By Topic

Sparse matrix computations: implications for cache designs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
V. E. Taylor ; EECS Dept., Northwestern Univ., Evanston, IL, USA

High-performance cache designs are studied for the class of sparse matrix computations, which are often excluded from the general programs used in previous cache studies. In particular, the data that should be stored in the cache are identified, and the cache organization is studied in terms of associativity, size, write operation, write policy, block size, and number of read and write ports. Simulation results demonstrate that a 1-kword or 8-kbyte (one word is equal to 64 b), direct-mapped cache produces good results with almost all of the misses occurring from first time accesses. This cache size can easily fit on a chip, with plenty of room to spare for other components

Published in:

Supercomputing '92., Proceedings

Date of Conference:

16-20 Nov 1992