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A speedup method of a high-speed direct-coupled Josephson logic gate

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5 Author(s)
Aoyagi, M. ; Electrotech. Lab., Ibaraki, Japan ; Nakagawa, H. ; Kurosawa, I. ; Akoh, H.
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The switching mechanism of a direct-coupled Josephson logic gate, a four-junction logic gate, has been investigated. It was found that a high-speed input signal current is wasted in an input-output separation resistance (R/sub i/). A speedup method has been developed in which an inductance is connected to (R/sub i/) in series. The value of the inductance was found to be five times larger than the effective inductance of the input junction. A speedup of 40% in the gate switching was demonstrated by a logic delay experiment using submicron NbN-MgO-NbN junction technology. The minimum logic delay of 3.0 ps/gate was obtained with fan-out 1.<>

Published in:

Applied Superconductivity, IEEE Transactions on  (Volume:3 ,  Issue: 1 )