A performance optimization tool for performance-driven micro-cell generation in sea-of-gates arrays

A performance-driven microcell compiler for sea-of-gates arrays is proposed. This compiler is responsible for the generation of the layout of small logical cells in a semicustom environment. One part of this compiler, the topology generator, is described in more detail. The performance optimization methods in the literature have been analyzed, together with their application to the topology generator. This has resulted in a set of 12 performance optimization heuristics. The influence of each heuristic on the performance parameters has been studied by circuit simulations and by qualitatively considering capacitive and resistive effects. Several performance optimizations have been carried out, demonstrating that it is possible to optimize microcells for different performance parameters.<
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