Referenced Items are not available for this document.
A 510-kG CMOS sea-of-gates (SOG) was experimentally developed using 0.6- mu m triple-metal-layer process technology and a 5-V/3.3-V interface. High-speed ASICs for high-performance processor systems supporting both TTL level and LVTTL level interfaces were developed. The 5-V/3.3-V interface concept employs a CMOS buffer on p-substrate, to choose an output high level of either 3.3 V or 5 V. The typical delay times of the internal gate and output buffer are 0.2 ns and 1.3 ns, respectively.<
Published in:
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Date of Conference: 4-6 June 1992
- Page(s):
- 88 - 89
- Meeting Date :
- 04 Jun 1992-06 Jun 1992
- Print ISBN:
- 0-7803-0701-1
- INSPEC Accession Number:
- 4437415
- Conference Location :
- Seattle, WA, USA
- Digital Object Identifier :
- 10.1109/VLSIC.1992.229290
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