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Sub-1-V swing bus architecture for future low-power ULSIs

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5 Author(s)
Nakagome, Y. ; Hitachi Ltd., Tokyo, Japan ; Itoh, K. ; Isoda, M. ; Takeuchi, K.
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Reducing the operating voltage is one of the most efficient ways to reduce the power dissipation of deep submicron ULSIs. A new bus architecture that reduces the operating power by using a bus signal swing of less than 1 V is proposed. This enables reduction of the bus swing to 1/3 that of the conventional architecture while maintaining a high speed and a low standby current. This architecture provides an efficient way to relieve the constraint of subthreshold leakage on V/sub CC/ scaling and to reduce the operating power of deep submicron ULSIs. Circuit configuration and performance are presented, together with experimental results.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992