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High-speed low-power Darlington ECL circuit

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4 Author(s)
Chuang, C.T. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Chin, K. ; Lu, P.F. ; Shin, H.J.

An emitter coupled logic (ECL) circuit with a Darlington configured dynamic current source and an active-pull-down emitter-follower stage for low-power high-speed gate array application is presented. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A self-biasing scheme for the dynamic current source and the active-pull-down transistor, with no additional devices and power in the biasing circuit, is described. Based on a 0.8- mu m double-poly self-aligned bipolar technology at a power consumption of 1.0-mW/gate, the circuit offers 28% improvement in the loaded delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992

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