By Topic

A low power 12 b analog-to-digital converter with on-chip precision trimming

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
deWit, M. ; Texas Instrum., Dallas, TX, USA ; Tan, K.S. ; Hester, R.K.

The design and performance of a 12 b charge redistribution ADC is described. The architecture is chosen to minimize conversion time and power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a linear 1 mu m CMOS process. The die area, including the 12 b parallel digital interface is 15 kmil/sup 2/. The power dissipation is under 15 mW, making the energy per conversion only 45 nJ.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992