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A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture

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5 Author(s)
T. Kobayashi ; Toshiba Corp., Kawasaki, Japan ; K. Nogami ; T. Shirotori ; Y. Fujimoto
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Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch sense amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror sense amplifier operation. The other is a static power saving input buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch sense amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992