Referenced Items are not available for this document.
The use of realistic structural and behavioral level descriptions of digital signal multiprocessors to find rate optimal and processor optimal schedules for implementation on multiprocessor digital signal processor (DSP) systems is addressed. Unlike previous work, the digital signal multiprocessor compiler (DSMP-C1) explicitly considers the location of operands, the number of accumulators and registers, the size of on-chip and external memories, the size of communication buffers, and inter-processor communications. The algorithm implicitly retimes and pipelines the flow graph and generates overlapping PSSIMD schedules that are both rate and processor optimal. When compared to previously published scheduling algorithms, the DSMP-C1 algorithm produces significantly shorter iteration periods
Published in:
Acoustics, Speech, and Signal Processing, 1992. ICASSP-92., 1992 IEEE International Conference on
(Volume:5
)
Date of Conference: 23-26 Mar 1992
- Page(s):
- 589 - 592 vol.5
- Meeting Date :
- 23 Mar 1992-26 Mar 1992
- ISSN :
- 1520-6149
- Print ISBN:
- 0-7803-0532-9
- INSPEC Accession Number:
- 4459792
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ICASSP.1992.226551
- Product Type:
- Conference Publications
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