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Decentralized arbiter design for a synchronous hierarchical bus multiprocessor system

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2 Author(s)
Alam, M.S. ; Dept. of Electr. Eng., Dayton Univ., OH, USA ; Karim, M.A.

A two-level decentralized bus arbitration network for a hierarchical bus system is developed. To achieve distributed control and ensure fairness among the competing processors, the rotating daisy chain implementation scheme is used in this design. The authors discuss the hierarchical bus system (HBS) architecture, the HBS arbitration algorithm, the generation of bus requests through the processor bus requests (PBR) generation circuitry, and the arbitration of requests of a bus memory arbiter (BMA). The proposed arbiter uses a simpler control mechanism by using distributed control and ensures fairness by dynamically changing the priorities of the devices connected to the bus. With this arbitration scheme, the HBS system is more efficient than a corresponding multiple bus system in terms of the number of transactions that can be carried out

Published in:

Aerospace and Electronics Conference, 1992. NAECON 1992., Proceedings of the IEEE 1992 National

Date of Conference:

18-22 May 1992