Referenced Items are not available for this document.
A CMOS VLSI chip set, which consists of three chips including a chip with 495000 transistors, 0.8-ns gate delay, and a 12-ns RAM, has been developed to achieve a high-performance 32-bit mainframe processor. This chip set uses a 1.2-μm double-diffused-drain transistor, double-layer metallization technology and a sophisticated CAD (computer-aided design) system. Each chip is mounted on a 288-pin surface-mount pin grid array package. A one-board CPU can be realized by assembling the chip set on a multilayer printed wiring board with RAMS and interface LSIs
Published in:
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Date of Conference: 16-19 May 1988
- Page(s):
- 24.6/1 - 24.6/4
- Meeting Date :
- 16 May 1988-19 May 1988
- INSPEC Accession Number:
- 3247430
- Conference Location :
- Rochester, NY
- Digital Object Identifier :
- 10.1109/CICC.1988.20929
- Product Type:
- Conference Publications
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