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Jitter attenuation phase locked loop using switched capacitor controlled crystal oscillator

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2 Author(s)
Shih, C.-C. ; Rockwell Int., Newport Beach, CA, USA ; Sun, S.Y.

A jitter attenuation, narrow-bandwidth phase-locked loop (PLL) consisting of a switched-capacitor controlled crystal oscillator (SCCXO) and a countdown sequential-logic phase/frequency detector (PFD) is described. By varying the loading capacitance dynamically, the SCCXO frequency is adjusted according to the duty cycle of the control signal. The experiment results show that a PLL of less than 2-Hz loop bandwidth and input jitter rejection up to 30 unit intervals is achieved in 3000 square mils of silicon area using 3- μm CMOS technology. The intrinsic jitter output is 0.03 UI

Published in:

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Date of Conference:

16-19 May 1988