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A fast offset-free sample-and-hold circuit

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2 Author(s)
Wang, F.-J. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; Temes, G.C.

A sample-and-hold stage is described that uses a CMOS cascode inverter and a novel switching scheme. Since the output voltage need not slew back to the Vos voltage level, the new circuit does not need to have an excessively high slew rate. The experimental results show that a high-speed and small-chip-area sample-and-hold circuit can be obtained when small-geometry (1-μm design rule) devices are available

Published in:

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Date of Conference:

16-19 May 1988