Referenced Items are not available for this document.
A BIST (built-in self test) methodology that uses the circular BIST technique to perform a random test of sequential logic circuits is presented. The fault coverage obtained using this technique is supplemented by deterministic tests that are presented to the CUT (circuit under test) by configuring the circular path as a partial scan chain. A CAD (computer-aided-design) tool for automating this methodology is described, a variety of heuristics for picking which flip-flops should be included in the circular path are evaluated, and experimental results are presented
Published in:
Test Conference, 1988. Proceedings. New Frontiers in Testing, International
Date of Conference: 12-14 Sep 1988
- Page(s):
- 719 - 729
- Meeting Date :
- 12 Sep 1988-14 Sep 1988
- ISSN :
- 1089-3539
- Print ISBN:
- 0-8186-0870-6
- INSPEC Accession Number:
- 3327227
- Conference Location :
- Washington, DC
- Digital Object Identifier :
- 10.1109/TEST.1988.207857
- Product Type:
- Conference Publications
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