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A 14-bit 80-kHz sigma-delta A/D converter: modeling, design and performance evaluation

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3 Author(s)
S. R. Norsworthy ; AT&T Bell Lab., Allentown, PA, USA ; I. G. Post ; H. S. Fetterman

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f/sub t/ were developed for the integrators. The circuit is implemented in a 1.75- mu m 5-V CMOS process. The analog circuitry occupies 2 mm/sup 2/ of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software.<>

Published in:

IEEE Journal of Solid-State Circuits  (Volume:24 ,  Issue: 2 )