Referenced Items are not available for this document.
A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO2 films formed over the abrupt topography of fine-line (2.0-μm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO2 must be maintained at ~0.4 (3800 and 9100 Å/min, respectively) with an Ar/CF4/O2 high pressure plasma generated in a low radio-frequency etching system
Published in:
Semiconductor Manufacturing, IEEE Transactions on
(Volume:1
,
Issue:
4
)
Date of Publication: Nov 1988
- Page(s):
- 154 - 156
- ISSN :
- 0894-6507
- INSPEC Accession Number:
- 3312918
- Digital Object Identifier :
- 10.1109/66.17989
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov 1988
- Sponsored by :
- IEEE Components, Packaging and Manufacturing Technology Society
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