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Planarization of dielectric layers for multilevel metallization

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2 Author(s)
Riley, Paul E. ; Schlumberger Palo Alto Res., CA, USA ; Castel, E.D.

A process to planarize low-pressure chemical-vapor deposition (LPCVD) SiO2 films formed over the abrupt topography of fine-line (2.0-μm pitch) integrated circuits with two levels of metallization and pillar interconnections has been developed with sacrificial photoresist and plasma etching using response-surface methodology. To produce flat dielectric surfaces with this topography, the ratio of the measured etch rate of photoresist to that of phosphorus-doped SiO2 must be maintained at ~0.4 (3800 and 9100 Å/min, respectively) with an Ar/CF4/O2 high pressure plasma generated in a low radio-frequency etching system

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:1 ,  Issue: 4 )