Referenced Items are not available for this document.
A new digital distortion calibration technique is demonstrated in a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC). Calibration parameters are obtained in a way similar to conventional digital gain calibration. The prototype ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. Using the proposed calibration method, a 15-dB improvement of the third-order harmonic rejection is achieved. The measured SNDR and SFDR are 71.6 and 82.3 dB, respectively
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
11
)
Date of Publication: Nov. 2006
- Page(s):
- 2417 - 2423
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 9159461
- Digital Object Identifier :
- 10.1109/JSSC.2006.882886
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 30 October 2006
- Issue Date :
- Nov. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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