Referenced Items are not available for this document.
The deterioration of operating margin and increasing leakage current in SRAM are becoming critical problems with the advance of process scaling. To solve these problems, we propose a low-power SRAM circuit using thin buried-oxide fully depleted silicon-on-insulator transistors. The back-gate bias is introduced to the SRAM circuits and acquires high operating margin and high-speed operation under low supply voltage. The leakage current in stand-by state is reduced. This SRAM achieves 30% faster writing time under low-voltage operation and 90% less stand-by power
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
11
)
Date of Publication: Nov. 2006
- Page(s):
- 2366 - 2372
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 9159455
- Digital Object Identifier :
- 10.1109/JSSC.2006.882891
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 30 October 2006
- Issue Date :
- Nov. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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