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Thick-Strained-Si/SiGe CMOS Technology with Selective-Epitaxial-Si Shallow-Trench Isolation (SES-STI)

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7 Author(s)
M. Miyamoto ; Micro Device Division, Hitachi, Ltd., 16-3, Shinmachi 6-chome, Ome-shi, Tokyo 198-8512, Japan Tel: +81-428-33-2033, Fax: +81-428-33-2161, E-mail: masafumi ; N. Sugii ; Y. Yoshida ; Y. Hoshino
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We developed a new bulk strained-Si/SiGe CMOS technology free from any Ge-related problems, which has a 90-110-nm strained-Si layer thicker than the limit at which misfit-dislocations occur, and a new shallow-trench isolation structure that has a selective-epitaxial Si layer to cover up the SiGe trench surface. This process has advantages in manufacturing compatibility with Si-CMOS process, low junction leakage current, and no reliability problems caused by Ge out-diffusion, with the same performance enhancement as thin (< 20 nm) strained-Si/SiGe

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2006 International SiGe Technology and Device Meeting

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