Referenced Items are not available for this document.
This paper describes a ratio-independent algorithmic ADC architecture that requires a single differential amplifier and a comparator. The prototype 12-bit, 41.67 kS/s ADC with an active die area of 0.055 mm2 is implemented in a 0.13mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 32 muW power dissipation, the ADC achieves 80 dB SFDR and 60 dB SNDR, resulting in a power FOM of 0.9 pJ/conversion
Published in:
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
Date of Conference: 0-0 0
- Page(s):
- 47 - 48
- Print ISBN:
- 1-4244-0006-6
- INSPEC Accession Number:
- 9177051
- Conference Location :
- Honolulu, HI
- Digital Object Identifier :
- 10.1109/VLSIC.2006.1705305
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
