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A Low-Jitter PLL and Repeaterless Clock Distribution Network for a 20Gb/s Link

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5 Author(s)

A 10GHz clock generation and distribution network for an 8-channel 20Gb/s/channel data transmitter is demonstrated in a 90nm 1.2V CMOS process. Jitter due to power supply and device noise is minimized with an LC VCO and repeaterless clock network. The performance of the forwarded-clock link degrades by only 4% due to plusmn5% supply noise at the transmitter. The LC VCO achieves supply noise sensitivity of 200MHz/V (0.02%-frequency/1%-supply noise) and short-term (8-symbol) rms jitter of 100fs. The clock distribution network delay sensitivity to supply noise is 36ps/V. The total clocking power is 408mW

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VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

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