Scheduled System Maintenance on December 17th, 2014:
IEEE Xplore will be upgraded between 2:00 and 5:00 PM EST (18:00 - 21:00) UTC. During this time there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

A High Dynamic Range CMOS Image Sensor with In-Pixel Floating-Node Analog Memory for Pixel Level Integration Time Control

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Sang-Wook Han ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon ; Seong-Jin Kim ; Jae-Hyuk Choi ; Kim, Choong‐Ki
more authors

In this paper we report a high dynamic range CMOS image sensor (CIS) with in-pixel floating-node analog memory for pixel level integration time control. Each pixel has different integration time based upon the amount of its previous frame illumination. We can implement true CDS technique to reduce reset noise without any additional hardware because we use a floating-node parasitic capacitor as an analog memory. In the fabricated test sensor, we could achieve the extended dynamic range by more than 42dB. To the best of our knowledge, this is the first report on the use of pixel-node parasitic capacitor as an analog memory for the extension of dynamic range

Published in:

VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Date of Conference:

0-0 0