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A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits

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15 Author(s)
S. Ohbayashi ; Renesas Technol. Corp., Itami ; M. Yabuuchi ; K. Nii ; Y. Tsukamoto
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We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 mum2 SRAM cell with a beta ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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