Integrating SHECS-Based Critical Sections with Hardware SMP Scheduler in TLP-CMPs

This document presents the concept of integrating the SHECS (shared explicit cache system)-based critical sections with SMP scheduler to obtain the efficient general purpose hardware mutual exclusion facility in the TLP-CMP (thread-level parallelism-chip multiprocessing) SMP (symmetric multiprocessing) architectures. There are presented two solutions - the first integrates the SHECS-based CS with software multi-queue SMP scheduler, the second integrates the SHECS-based CS with hardware multi-queue SMP scheduler implemented as an additional functional unit within the TLP-CMP. The both propositions are implemented and simulated with using SoC (system-on-chip) such as Intelreg IXP 2800 network processor. The results of prove-of-concept simulation (obtained with the IXA SDK 4.2 Workbench simulation environment) are presented and discussed in this document