Referenced Items are not available for this document.
A novel partial-product reduction circuit for use in integer multiplication is presented. The high-performance multiplier (HPM) reduction tree has the ease of layout of a simple carry-save reduction array, but is in fact a high-speed low-power Dadda-style tree having a worst-case delay which depends on the logarithm (O(log TV)) of the word length N
Published in:
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Date of Conference: 21-24 May 2006
- Page(s):
- 4 pp. - 8
- Print ISBN:
- 0-7803-9389-9
- INSPEC Accession Number:
- 9086323
- Conference Location :
- Island of Kos
- Digital Object Identifier :
- 10.1109/ISCAS.2006.1692508
- Product Type:
- Conference Publications
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