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Digit-serial/parallel multipliers with improved throughput and latency

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2 Author(s)
M. Karlsson ; Dept. of Technol., Kalmar Univ., Sweden ; M. Vesterbacka

Digit-serial/parallel multipliers with improved throughput and latency are presented. The multipliers are based on unfolded bit-serial/parallel multipliers. The unfolding yields long critical paths that are reduced by splitting the multiplication as a sum of partial multiplications. Using a sum of two partial multiplications yields an increased throughput with between 50 and 120 percent and the latency is reduced with up to 50 percent, compared with the basic digit-serial/parallel multiplier based on unfolding

Published in:

2006 IEEE International Symposium on Circuits and Systems

Date of Conference:

21-24 May 2006