Scheduled System Maintenance:
On April 27th, single article purchases and IEEE account management will be unavailable from 2:00 PM - 4:00 PM ET (18:00 - 20:00 UTC).
We apologize for the inconvenience.
By Topic

Hierarchical bottom-up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
5 Author(s)
Eeckelaert, T. ; Katholieke Universiteit Leuven ; Schoofs, R. ; Gielen, G. ; Steyaert, M.
more authors

This paper describes key points and experimental validation in the development of a bottom-up hierarchical, multi-objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous-time DeltaSigma A/D converter for WLAN applications, to generate a set of Pareto-optimal design solutions. The generated performance tradeoff offers the designer access to a set of optimal design solutions, from which the designer can choose a satisfactory design point according to the performance specifications. The presented method takes advantage of the Pareto-optimal performance solutions of the hierarchical lower-level sub-blocks to generate the overall Pareto-optimal set at system level. The way the lower-level performance tradeoffs are combined and propagated to higher hierarchical levels, is one of the major key points in the bottom-up methodology. The experimental results validate the methodology for a 7-block hierarchical decomposition of a complex high-speed Delta;Sigma A/D modulator for a WLAN 802.11a/b/g standard

Published in:

Design Automation Conference, 2006 43rd ACM/IEEE

Date of Conference:

0-0 0