By Topic

Statistical approach for improving manufacturing yield in advanced IC fabrication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
A. C. Carlson ; Motorola Inc.. Mesa, AZ, USA ; S. L. Sundaran

The methods of planned experimentation, statistical error propagation, multi-vari and Pareto are discussed in terms of scaled-high-voltage analog BiMOS technology and advanced analog IC manufacturing. Applications of statistical techniques using response surface methodology, planned experimentation, statistical-error propagation, multi-vari and Pareto analysis are shown to enhance the definition, optimization, and resolution of complex processing and device problems. The multidisciplinary approach, which involves statistics, device physics, process characterization, device characterization, and manufacturing, plays a major role in the introduction of new IC technology and yield improvements in IC products. The case studies presented demonstrate the essential need for a statistical approach to solve complex IC manufacturing problems

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 1991. ASMC 91 Proceedings. IEEE/SEMI 1991

Date of Conference:

21-23 Oct 1991