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Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond

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6 Author(s)
Xiaoning Qi ; Direct Silicon Access Lab., Synopsys Inc., Mountain View, CA, USA ; A. Gyure ; Yansheng Luo ; S. C. Lo
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The on-chip inductive impact on signal integrity has been a problem for designs in deep-submicrometer technologies. The inductive impact increases the clock skew, max timing, and noise of bus signals. In this letter, circuit simulations using silicon-validated macromodels show that there is a significant inductive impact on the signal max timing (~ 10% pushout versus RC delay) and noise (~2timesRC noise). In nanometer technologies, process variations have become a concern. Results show that device and interconnect process variations add ~ 3% to the RLC max-timing impact. However, their impact on the RLC signal noise is not appreciable. Finally, inductive impact in 65- and 45-nm technologies is investigated, which indicates that the inductance impact will not diminish as technology scales

Published in:

IEEE Electron Device Letters  (Volume:27 ,  Issue: 8 )