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Browse Journals & Magazines > Electron Device Letters, IEEE ...> Volume:27 Issue:8 Help

Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

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10 Author(s)
van Dal, M.J.H. ; Philips Res. Eur., Leuven ; Boccardi, G. ; Veloso, A. ; Locorotondo, S.
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Short gate-length Pt full-silicidation (FUSI) (PtSi and Pt2 Si) pMOSFETs were fabricated for the first time using a self-aligned Pt-FUSI process, demonstrating scalability (with no linewidth effects) down to ~ 60-nm gate lengths. The electrical results are compared to the Ni-FUSI (NiSi and Ni31Si12) pMOSFET devices. A low threshold voltage les|-0.29 V| was obtained for the Pt2Si-FUSI pMOSFETs on SiON and HfSiON indicating that the Pt2Si FUSI does not suffer from the Fermi-level pinning or gate-dielectric-charge effects on the HfSiON

Published in:
Electron Device Letters, IEEE  (Volume:27 ,  Issue: 8 )

Date of Publication: Aug. 2006

Page(s):
665 - 667
ISSN :
0741-3106
INSPEC Accession Number:
9011153
Digital Object Identifier :
10.1109/LED.2006.878051
Product Type:
Journals & Magazines
Date of Current Version :
24 July 2006
Issue Date :
Aug. 2006
Sponsored by :
IEEE Electron Devices Society

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