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Parallel scrambler for high-speed applications

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5 Author(s)
Chih-Hsien Lin ; Dept. of Electr. Eng., Nat. Central Univ., Jung-Li City, Taiwan ; Chih-Ning Chen ; You-Jiun Wang ; Ju-Yuan Hsiao
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In order to improve the speed limitation of serial scrambler, we propose a new parallel scrambler architecture and circuit to overcome the limitation of serial scrambler. A very systematic parallel scrambler design methodology is first proposed. The critical path delay is only one D-register and one xor gate of two inputs. Thus, it is superior to other proposed circuits in high-speed applications. A new DET D-register with embedded xor operation is used as a basic circuit block of the parallel scrambler. Measurement results show the proposed parallel scrambler can operate in 40 Gbps with 16 outputs in TSMC 0.18-μm CMOS process.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 7 )

Date of Publication:

July 2006

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