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An in-place architecture for the deblocking filter in H.264/AVC

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3 Author(s)
Chao-Chung Cheng ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Tian-Sheuan Chang ; Kun-Bin Lee

This brief presents an in-place computing design for the deblocking filter used in H.264/AVC video coding standard. The proposed in-placed computing flow reuses intermediate data as soon as data is available. Thus, the intermediate data storage is reduced to only the four 4 × 4 blocks instead of whole 16 × 16 macroblock. The resulting design can achieve 100 MHz with only 13.41K gate count and support real-time deblocking operation of 2K × 1K@30 Hz video application when clocked at 73.73 MHz by using 0.25-μm CMOS technology.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 7 )

Date of Publication:

July 2006

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