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All digital, 1 GHz, clock phase control circuit

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1 Author(s)
Sauter, Gerald F. ; Unisys Corp., St. Paul, MN, USA

The author describes a novel method for solving the problem of interconnectivity for a pulse code modulation (PCM) system using a distributed master clock. This system requires that two digital data streams, coming from two stations and each operating at 0.5 to 1.0 Gb/s, with unknown clock phases be combined into one data stream and sent to a third station. The clock signals are all generated by a master clock and sent to each station, where they are recovered and used to encode the data from each station. The transit time plus the variation in transit time to each station is different and uncontrolled. The demonstrated solution involves comparing the phase of the clock from the returning data stream with the master clock phase and adjusting a phasing delay accordingly. An all-digital implementation of this solution was fabricated and operated at frequencies in excess of 1 GHz with a phase resolution of 120 ps

Published in:

Aerospace and Electronics Conference, 1991. NAECON 1991., Proceedings of the IEEE 1991 National

Date of Conference:

20-24 May 1991