Fine pitch (150/spl mu/m) Pb-free flip chip bumping and packaging

In the area of flip chip, even with high I/O ASICs, the die area has been large enough to support the I/O requirements using a 200-225 /spl mu/m pitch. In this range of bump pitches, there is a considerable base of data and experience. As the industry approaches the 65nm technology node, the die size is now shrinking to the point where many industry leaders require a significant reduction in bump pitch to meet their I/O requirements. At the same time, the push for Pb-free assemblies is continuing. Even with the current exemptions for FC internal bump connections, the 65nm node is ramping into peak production as these exemptions near their expiration. This presents the current challenge for flip chip. In order to satisfy the needs of the 65nm devices, a flip chip packaging solution capable of supporting fine pitch, Pb-free bump metallurgy, 245-260/spl deg/C reflow peaks, and long term reliability must be found. This paper explores some of the early evaluation work of this new system. The test vehicle used is a die of approximately 15mm fabricated using 65nm low-k technology incorporating a 150/spl mu/m pitch bump array. The bump size is designed to accommodate one escape of routing between the bumps on the top metal layer of the laminate usually referred to as Layer 1. The laminate used is a 42.5mm square laminate with a 400/spl mu/m thick core and a 4-2-4 (10 layer) build-up structure. The data presented here provides a baseline for current material set and process feasibilities to support these new geometries.