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A systematic approach to qualification of 90 nm low-K flip-chip packaging

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6 Author(s)
U. Vissa ; Avago Technol., Fort Collins, CO, USA ; N. Butel ; J. Rowatt ; C. Thielen
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Challenges associated with low-K flip-chip packaging arise from properties inherent with the dielectric material properties, i.e., lower strength, lower adhesions, and higher TCE (as compared to FSG dielectrics). In order to assemble and qualify a reliable and robust package, a lot of attention needs to be focused on items like material selection, bump type and bump distribution. This paper explains the step by step approach taken by Avago Technologies Imaging Systems Division (ISD), in partnership with Amkor Technology to successfully qualify a production ready process for 90 nm low-K flip chip using both ceramic HITCE and built-up laminate substrate technologies. This was implemented successfully on a new set of advanced laminate material with stacked vias and via on plated thru hole and eliminated electroless nickel immersion gold (ENIG) surface finish. Details of the test vehicles used and the test programs have been provided as well. The experiments will be discussed in detail, along with the assembly process steps and the underfills used, focusing on the properties that are important to stress reduction. The reliability test results - JEDEC for the component level tests (pop corning, temperature cycle, high temperature storage and biased HAST) are also presented. The process robustness was addressed by extending the reliability test read points to 2000 temperature cycles and 2000 hours of high temperature storage. Failure analysis results will be discussed where appropriate. Finally, the qualification results with the frozen process are presented and discussed

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56th Electronic Components and Technology Conference 2006

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