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A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

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2 Author(s)
Caldwell, T.C. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont. ; Johns, D.A.

This paper presents the first implementation results for a time-interleaved continuous-time DeltaSigma modulator. The derivation of the time-interleaved continuous-time DeltaSigma modulator from a discrete-time DeltaSigma modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass DeltaSigma modulator is designed in a 0.18-mum CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively

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Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 7 )