Referenced Items are not available for this document.
In this paper, we summarize how the introduction of SIMS structures near the global alignment marks of product wafers serve as an additional way to acquire detailed analytical information about front-end processing and can minimize product yield loss without waiting for metal 1 processing when electrical testing (ET) becomes possible
Published in:
Advanced Semiconductor Manufacturing Conference, 2006. ASMC 2006. The 17th Annual SEMI/IEEE
Date of Conference: 22-24 May 2006
- Page(s):
- 17 - 20
- ISSN :
- 1078-8743
- Print ISBN:
- 1-4244-0254-9
- INSPEC Accession Number:
- 9085361
- Conference Location :
- Boston, MA
- Digital Object Identifier :
- 10.1109/ASMC.2006.1638717
- Product Type:
- Conference Publications
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