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Low-power programmable gain CMOS distributed LNA

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2 Author(s)
Zhang, F. ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Kinget, P.R.

A design methodology for low power MOS distributed amplifiers (DAs) is presented. The bias point of the MOS devices is optimized so that the DA can be used as a low-noise amplifier (LNA) in broadband applications. A prototype 9-mW LNA with programmable gain was implemented in a 0.18-μm CMOS process. The LNA provides a flat gain, S21, of 8 ± 0.6dB from DC to 6.2 GHz, with an input impedance match, S11, of -16 dB and an output impedance match, S22, of -10 dB over the entire band. The 3-dB bandwidth of the distributed amplifier is 7GHz, the IIP3 is +3 dBm, and the noise figure ranges from 4.2 to 6.2 dB. The gain is programmable from -10 dB to +8 dB while gain flatness and matching are maintained.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 6 )

Date of Publication:

June 2006

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