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All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles

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3 Author(s)
You-Jen Wang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Shao-Ku Kao ; Shen-Iuan Liu

An all-digital delay-locked loop (DLL) and an all-digital pulsewidth-control loop (PWCL) with adjustable duty cycles are presented. For the DLL, by using the flash time-to-digital conversion, both the phase alignment and the duty cycle of the output clock are assured in 10 cycles. For the PWCL, the sequential time-to-digital conversion is adopted to reduce the required D-flip-flops and lock within 28 cycles. For both of the proposed circuits, the requirement of the input clock with 50% duty cycle is eliminated. The proposed circuits have been fabricated in a 0.35-μm CMOS process. The proposed DLL generates the output clock with the duty cycle of 25%, 50% and 75%, and the operation frequency range is from 140 to 260 MHz. For the proposed PWCL, the duty cycle is adjusted from 30% to 70% in steps of 10%. The operation frequency range is from 400 to 600 MHz.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 6 )

Date of Publication:

June 2006

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