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Integrated Verification Approach during ADL-Driven Processor Design

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6 Author(s)
A. Chattopadhyay ; Aachen University of Technology, Germany ; A. Sinha ; Diandian Zhang ; R. Leupers
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Nowadays, architecture description languages (ADLs) are getting popular to achieve quick and optimal design convergence during the development of application specific instruction-set processors (ASIPs). Verification, in various stages of such ASIP development, is a major bottleneck hindering widespread acceptance of ADL-based processor design approach. Traditional verification of processors are only applied at register transfer level (RTL) or below. In the context of ADL-based ASIP design, this verification approach is often inconvenient and error-prone, since design and verification are done at different levels of abstraction. In this paper, this problem is addressed by presenting an integrated verification approach during ADL-driven processor design. Our verification flow includes the idea of automatic assertion generation during high-level synthesis and support for automatic test-generation utilizing the ADL-framework for ASIP design. We show the benefit of our approach by trapping errors in a pipelined SPARC-compliant processor architecture

Published in:

Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)

Date of Conference:

14-16 June 2006