Delay modeling using ramp and realistic signal waveforms

Accurate estimation of circuit delay has become a primary requirement to ensure the correct synchronization of high speed synchronous integrated circuits. In this paper, the difference in circuit delay simulated using ramp and realistic signal waveforms is investigated. It is shown that the realistic signal waveform produces larger delay estimates than the ramp waveform. Ramp and realistic waveforms are also used to characterize circuit cells and acquire close delay approximations using static timing analysis. Finally, noise effects that introduce variations in circuit delay are considered. Variations in delay due to these effects are calculated using ramp and realistic signal waveforms.